The field of the invention is that of integrated circuit fabrication, including CMOS transistors formed with strained silicon for higher mobility.
An important aim of ongoing research in the semiconductor industry is increasing semiconductor performance while decreasing the size of semiconductor devices. Planar transistors, such as metal oxide semiconductor field effect transistors (MOSFET) are particularly well suited for use in high-density integrated circuits.
Strained silicon technology allows the formation of higher speed devices. Strained-silicon transistors are created by depositing a graded layer of silicon germanium (SiGe) on a bulk silicon wafer. The top part of the SiGe layer is relaxed SiGe. A thin layer of silicon is subsequently deposited on the SiGe layer. The crystalline structure of SiGe is diamond which is the same as silicon (Si). The lattice constant in the SiGe is greater than that in Si. If the thickness of a strained Si or SiGe layer is smaller than a critical thickness, the stress in the strained layer can be maintained and dislocations are not generated. Therefore, when a thin silicon layer (thinner than critical thickness) is deposited on top of SiGe the silicon crystal lattice tends to stretch or “strain” to align the silicon atoms with the atoms in the SiGe layer. Electrons in the strained silicon experience less resistance and flow up to 80% faster than in unstrained silicon.
There are two general types of MOS transistors, N-channel MOS (NMOS) formed with n-type source and drain regions in a p-type region of silicon, and P-channel MOS (PMOS) formed with p-type source and drain regions in an n-type region of silicon. NMOS transistors conduct electrons through the transistor channel, while PMOS transistors conduct holes through the transistor channel. Typically, the source and drain regions of the transistors are doped with phosphorous or arsenic to form n-type source/drain regions, while boron doping is used to form p-type source/drain regions.
CMOS transistors, which comprise N- and P-channel MOS transistors on the same substrate, suffer from imbalance. The imbalance is due to electron mobility being greater than hole mobility in the channel region. Therefore, NMOS transistors are faster than PMOS transistors. Typically, NMOS transistors are about 2 to about 2.5 times faster than PMOS transistors.
A particular aspect of strained silicon NMOS transistors that have SiGe under the strained silicon is that the external resistance of an NMOS transistor is greater than the exterior resistance of a corresponding/conventional NMOS transistor.
Various approaches in circuit design have been developed to compensate for the difference in transistor operating speed or to exploit the higher speed of NMOS transistors.
There exists a need in the semiconductor device art to provide NMOS transistors on strained silicon that have external resistance that is closer to that of unstrained/conventional transistors. Experimental data show that a strained Si/SiGe NFET has larger external resistance than a conventional Si NFET, although the channel resistance of strained Si/SiGe NFET is smaller than that in a Si NFET. Therefore, a preferable structure for a high performance NFET is that of a strained Si channel with the source/drain and extension being formed in pure silicon. This gives both small external resistance and small channel resistance. Our invention provides structures and methods for making such NFETs.
The term semiconductor devices, as used herein, is not to be limited to the specifically disclosed embodiments. Semiconductor devices, as used herein, include a wide variety of electronic devices including flip chips, flip chip/package assemblies, transistors, capacitors, microprocessors, random access memories, etc. In general, semiconductor devices refer to any electrical device comprising a semiconductor.